This invention relates to three-phase voltage-source inverters, and more particularly relates to a method and apparatus for sensing phase current with shunt resistors on inverter legs.
Pulse width modulation (PWM) techniques are used to control three-phase (3xcfx86) voltage-source inverters (VSI), in applications such as control of DC brushless, AC induction motors, permanent-magnet synchronous motors, and other 3xcfx86 loads. For example, PWM inverters make it possible to control both the frequency and magnitude of the voltage and current applied to a motor. As a result, PWM inverter-powered motor drives offer better efficiency and higher performance compared to fixed frequency motor drives. The energy that a PWM inverter delivers to a load is controlled by PWM signals applied to the gate or base of the power transistors.
Several PWM techniques are known and used in the art, for determining the modulating signal and the switch-on/switch-off instants from the modulating signal. Currently popular examples are sinusoidal PWM, hysteric PWM, and space-vector (SV) PWM. These techniques are commonly used for control of AC induction, BLDC and switched reluctance (SR) motors.
PWM can be either symmetric, or asymmetric, as shown in FIG. 1. In FIG. 1 two pulse waveforms 10 and 12, are shown for four contiguous, equal periods. The top waveform 10 in the figure is an example of an asymmetric PWM, in which the timing for the leading edge in each period varies, as shown by arrow 14, while the trailing edge always coincides with the end of the period. The bottom waveform 12 in the figure is an example of a symmetric PWM, in which the timing for both the leading edge and the trailing edge is varied by the same amount in opposite directions, as shown by arrows 16 and 18, respectively, resulting in symmetry for the waveform in every period.
A circuit diagram of a typical 3xcfx86 VSI 20 is shown in FIG. 2. A DC voltage, VDC, is provided between a V+BUS 22 and a Vxe2x88x92BUS 24. Three legs are connected between bus 22 and bus 24. The first leg includes a power transistor Q1 having its collector connected to bus 22, and a power transistor Q2 having its collector connected to the emitter of transistor Q1 and having its emitter connected to bus 24. A diode D1 is connected between the emitter and collector of transistor Q1, and a diode D2 is connected between the emitter and collector of transistor Q2. In both cases the cathode of the diode is connected to the collector of the transistor. A control signal a is provided on line 26 to the base of transistor Q1, while a control signal axe2x80x2 is provided on line 28 to the base of transistor Q2. The common connection point of transistors Q1 and Q2 is connected to line 38, which carries the output voltage Va and phase a current ia of the first leg.
The other two legs are of the same structure as the first leg. Thus, the second leg includes a power transistor Q3 having its collector connected to bus 22, and a power transistor Q4 having its collector connected to the emitter of transistor Q3 and having its emitter connected to bus 24. A diode D3 is connected between the emitter and collector of transistor Q3, and a diode D4 is connected between the emitter and collector of transistor Q4. In both cases the cathode of the diode is connected to the collector of the transistor. A control signal b is provided on line 30 to the base of transistor Q3, while a control signal bxe2x80x2 is provided on line 32 to the base of transistor Q4. The common connection point of transistors Q3 and Q4 is connected to line 40, which carries the output voltage Vb and phase b current ib of the second leg.
Similarly, the third leg includes a power transistor Q5 having its collector connected to bus 22, and a power transistor Q6 having its collector connected to the emitter of transistor Q5 and having its emitter connected to bus 24. A diode D5 is connected between the emitter and collector of transistor Q5, and a diode D6 is connected between the emitter and collector of transistor Q6. In both cases the cathode of the diode is connected to the collector of the transistor. A control signal c is provided on line 34 to the base of transistor Q5, while a control signal cxe2x80x2 is provided on line 36 to the base of transistor Q6. The common connection point of transistors Q5 and Q6 is connected to line 42, which carries the output voltage Vc and phase c current ic of the third leg.
In operation, when an upper transistor, Q1, Q3 or Q5, is turned on, i.e., when a, b or c is 1, the corresponding lower transistor, Q2, Q4, or Q5, is switched off, i.e., the corresponding axe2x80x2, bxe2x80x2 or cxe2x80x2 is 0. The on and off states of the upper transistors are sufficient to evaluate the output voltage for the purposes of this discussion. The relationship between the switching variable vector [a, b, c], the line-to-line output voltage vector [Vab Vbc Vca] and the phase (line-to-neutral) output voltage vector [Van Vbn Vcn], for a balanced load, is given by the following equations:                               [                                                                      V                  ab                                                                                                      V                  bc                                                                                                      V                  ca                                                              ]                =                              [                                                            1                                                                      -                    1                                                                    0                                                                              0                                                  1                                                                      -                    1                                                                                                                    -                    1                                                                    0                                                  1                                                      ]                    ⁡                      [                                                            a                                                                              b                                                                              c                                                      ]                                              Equation   (1)                                          [                                                                      V                  bn                                                                                                      V                  bn                                                                                                      V                  cn                                                              ]                =                              [                                                            2                                                                      -                    1                                                                                        -                    1                                                                                                                    -                    1                                                                    2                                                                      -                    1                                                                                                                    -                    1                                                                                        -                    1                                                                    2                                                      ]                    ⁡                      [                                                            a                                                                              b                                                                              c                                                      ]                                              Equation   (2)            
where VDC is the DC supply voltage, or the bus voltage.
There are eight possible combinations of on and off states for the three upper power transistors. The eight combinations and the derived output line-to-line and phase voltages in terms of DC supply voltage VDC, according to Equation (1) and Equation (2), are shown in Table 1:
Assume d and q are the fixed horizontal and vertical axes in the plane of the three motor phases. The vector representations of the phase voltage corresponding to the eight combinations can be obtained by applying the following so-called d-q transformation to the phase voltages:                               T                      abc            -            dq                          =                                            2              3                                ⁡                      [                                                            1                                                                      -                                          1                      2                                                                                                            -                                          1                      2                                                                                                                    0                                                                                            3                                        2                                                                                        -                                                                  3                                            2                                                                                            ]                                              Equation        ⁢                  xe2x80x83                ⁢                  (          3          )                    
This transformation is equivalent to an orthogonal projection of [a,b,c] onto the two dimensional plane having perpendicular axes d axis 50 and q axis 52, perpendicular to the vector [1,1,1] in a three-dimensional coordinate system, the results of which are six non-zero vectors and two zero vectors as shown in FIG. 3. The six non-zero vectors form the axes of a hexagonal 54 having six sectors 56, 58, 60, 62, 64 and 66, each bounded by two of the non-zero vectors. The angle between any adjacent two non-zero vectors is 60 degrees. The zero vectors are at the origin of axes 50, 52, and apply zero voltage to the three-phase load. The eight vectors are called the basic space vectors and are denoted in FIG. 3 by U0, U60, U120, U180, U240, U300, O000, and O111.
The same d-q transformation can be applied to a desired three-phase voltage output to obtain a desired reference voltage vector uout in the d-q plane as shown in FIG. 3. In general, the vector uout has a magnitude of ∥uout∥ and an angle of xcex1 with respect to one of the two basic vectors forming the sector that contains uout in an instant of time. Being in the sector 56 bounded by space vectors U0 and U60, the particular vector uout shown in FIG. 3 may be expressed as the vector sum of two vector components u1 and u2, having the same angle as space vectors U0 and U60, respectively. Note that the magnitude of uout is the root mean square (rms) value of the corresponding line-to-line voltage with the defined d-q transform. Note also that the maximum magnitude for uout, shown in FIG. 3 as uoutmax, can be derived to be             V      DC              2        .
In operating a 3xcfx86 VSI such as 3xcfx86 VSI 20 of FIG. 1, it is important to control the phase currents ia, ib and ic, so as to control, e.g., the torque and speed of a motor load. The objective of the present invention is low cost monitoring of this xe2x80x9cphase current.xe2x80x9d
The easiest way in which to monitor phase current is with a transformer coupled circuit. A hall effect sensor is typically used when this type of monitoring is chosen. However, such monitors are costly, requiring typically a transformer and separate integrated circuit. In addition, the signal output of such monitors requires a linear amplifier, which adds design complexity and further cost.
Another approach uses a so-called shunt resistor. An example of this is shown in FIG. 4, which is a diagram of the second, Q3, Q4 leg of the 3xcfx86 VSI 20 of FIG. 2, having the shunt resistor RS, connected between the emitter of transistor Q4 and Vxe2x88x92BUS 24. Each of the three legs is provided with such a resistor. In using this technique the voltage vS across RS is measured when transistor Q4 is on, and Ohms Law applied to derive the current iS, or phase current ib, through resistor RS. Now, the duty cycle of the particular leg determines the amount of time that the lower transistor in that leg, e.g., transistor Q4, is on. Ignoring dead band effects, if the duty cycle of a leg is dcy, expressed as a decimal quantity with a 0% duty cycle being represented as 0 and a 100% duty cycle being represented as 1.0, and the PWM period being represented as TPWM, then the upper transistor is on dcy* TPMW, and the lower transistor is on (1xe2x88x92dcy)* TPWM.
It is necessary for the width of the lower leg pulse, or, sampling interval, to be sufficiently long to have a xe2x80x9cgoodxe2x80x9d sample to measure. This is because reactive components at the base of the lower leg transistor will subject the voltage at that node to a time constant factor, delaying the achievement of the full voltage, causing ringing, and the like. The so-called dead band included to prevent shoot through fault also reduces the effective sampling interval. Thus, the pulse width must be sufficiently long to take into account the dead band and still allow the measured voltage to settle, and thus correspond to the true phase current.
One prior art approach to dealing with this problem has been to xe2x80x9cover-designxe2x80x9d the inverter, so that the on time for the lower transistor e.g., transistor Q4, is never smaller than a lower bound. In other words, the inverter components are designed to provide a high enough voltage so that the upper transistor in any leg is never on for such a high portion of a PWM period that the lower transistor is on for such a short time that a good sample of the voltage vS cannot be taken.
Still, it is desired to have a lower cost solution to providing an accurate phase current monitor for a 3xcfx86 VSI, while not requiring, e.g., over-design of the inverter. The present invention provides such a lower cost solution.
The present invention provides, in a pulse width modulation controlled three-phase voltage-source inverter having three legs, each leg including two transistors coupled serially between the terminals of a power source and providing a respective drive output, each leg further including a shunt resistor between one of the two transistors and one of the terminals, in which control pulses are applied to each leg during a sequence of pulse periods, and the inverter has a neutral current, a method for determining the phase current for each leg. The method includes the following steps. First, it is determined which two legs have the longest on time for the lower power transistors. The current through the shunt resistors for the determined legs is determined, to obtain a value representative of the phase current for the legs. Finally, the phase current for the leg not sampled during the sector is derived by subtracting the determined phase currents from the neutral current.
These and other features of the invention will be apparent to those skilled in the art from the following detailed description of the invention, taken together with the accompanying drawings.